1. Field of the Invention:
This invention relates to a method of forming contact windows and more particularly to a method of forming contact windows in an insulating layer which is deposited over metal layers in a fabrication process of semiconductor devices having a multi-level interconnection structure.
2. Description of the Prior Art:
Semiconductor integrated circuit devices comprise fine line patterns of wiring layer for electrically interconnecting transistors and other circuit elements formed on a semiconductor substrate. As the number of circuit elements integrated on the semiconductor substrate increases, the size of the circuit elements and the distance between the circuit elements become smaller and smaller. Semiconductor devices having a multi-level interconnection structure are being developed to facilitate interconnection between such high density circuit elements.
FIG. 4 shows a cross sectional view of a fragmentary portion of a semiconductor device having a two-level interconnection structure. The semiconductor device shown in FIG. 4 comprises a silicon substrate 30, isolation oxides 31 formed in isolation regions on the surface of the silicon substrate 30, MOSFETs 36a and 36b formed in element regions on the silicon substrate 30, a first insulating layer 32 which covers the MOSFETs 36a and 36b, first metal layer 33 for interconnecting the MOSFETs 36a and 36b and so on, a second insulating layer 34 which covers the first metal layer 33, and second metal layer 35 formed on the second insulating layer 34.
The MOSFETs 36a and 36b each comprise impurity diffusion layers (functions as source and drain) 38 formed in prescribed parts of the element regions of the silicon substrate 30, the gate oxide 39 formed on the element region, and the gate electrode 41 formed on the gate oxide 39.
The first metal layer 33 and the second metal layer 35 are in contact with each other through contact windows 40 formed at prescribed regions in the second insulating layer 34.
The prior art method of forming the contact windows 40 in the second insulating layer 34 is described below. The second insulating layer 34 is deposited over the silicon substrate 30 so it covers the first metal layer 33. A CVD method is used as a deposition method. A photoresist layer (not shown) which functions as an etching mask layer is then formed on the second insulating layer 34, after which contact regions of the photoresist layer are removed by a usual photolithography method. Thus, the etching mask layer (photoresist layer) having openings for defining contact window regions of the insulating layer 34 is formed on the insulating layer 34.
An etching process is then performed using an etching gas, thereby etching away the contact window regions of the second insulating layer 34 through the openings of the etching mask layer to form the contact windows. Those parts of the second insulating layer 34 covered by the photoresist do not come in contact with the etching gas due to the presence of the etching mask, so they are not etched.
The etching process is explained in greater detail below. The etching gas used in the etching process is selected based on the material of the insulating layer 34. For example, if the insulating layer 34 is made from silicon dioxide (SiO.sub.2), a mixed gas containing CHF.sub.3, C.sub.2 F.sub.6, O.sub.2 and He would be selected.
The etching process is performed using an RIE apparatus or other type of etching apparatus. When performing the etching process with a high anisotropy, the etching gas is partially ionized by a discharge between the electrodes in the etching apparatus and changed to a plasma.
FIG. 5 shows a mechanism of a contact window formation in the second insulating layer 34 by the etching process using the etching gas plasma. As shown in FIG. 5, ions generated in the etching gas plasma are accelerated across the sheath potential (not shown) toward the silicon substrate 30, and the ions bombard the photoresist 37 and the second insulating layer 34 over the silicon substrate 30. A contact window region of the second insulating layer 34 not covered by the photoresist layer 37 are effectively etched with the assistance of the ions. The energy of the ions accelerated across the sheath potential depends on the RF power of the discharge, since the sheath potential is generated by the discharge.
As the etching progresses, a polymer film (deposit 38) containing carbon atoms is deposited on the side wall of the contact window 40 and the photoresist 37. Especially, if the second insulating layer 34 is a TEOS layer formed from TEOS (tetraethyl orthosilicate), the high carbon content of the TEOS layer causes a thick accumulation of deposit 38 to form. The presence of the deposited film 38 prevents etching of the side wall of the contact window 40. Therefore, the etching of the second insulating layer 34 progresses perpendicularly to the surface of the silicon substrate 30 through the opening of the photoresist 37, thus facilitating the formation of contact windows with a high aspect ratio.
The above method of forming contact windows results in sputtering of the surface of the first metal layer 33 by the ions after the surface has been exposed to ion bombardment through the contact window 40. The metal or metal compounds sputtered from the surface of the first metal layer 33 are implanted into the photoresist 37 near the contact window 40 or the deposit 38 on the side wall of the contact window 40. This causes the surfaces of the photoresist 37 and the deposit 38 to harden. The photoresist 37 or deposit 38 whose surface has become hardened is difficult to remove from the wafer. Therefore, the hardened photoresist 37 or deposit 38 remains near the contact window 40 even after a resist-removing process for removing the photoresist 37 by using O.sub.2 plasma ashing technique and a cleaning process for cleaning the surface of the silicon substrate 30 are performed.
FIG. 3 shows the deposits 38 remaining near the contact windows 40. This is an is perspective view drawn from scanning electron micrographs. The contact windows 40 in FIG. 3 are formed in the second insulating layer 34 (made of a TEOS layer) covering the first wiring layer 33 (made of aluminum). The etching of the second insulating layer 34 performed by using an etching gas mixture of CHF.sub.3, O.sub.2 and He to form the contact windows. The flow rates of CHF.sub.3, O.sub.2 and He were 90 sccm, 10 sccm and 100 sccm, respectively.
The etching apparatus used was a normal reactive ion etching (RIE) apparatus. The etching was performed over the period of time it would take to etch an insulating layer 1.5 times thicker than the second insulating layer 34. This type of etching is referred to as "50% over-etching".
As shown in FIG. 3, hardened deposits 38 remain inside and around the contact windows 40. The deposits 38 degrades the interconnection between the second metal layer 35 and the first metal layer 33 via the contact windows 40. This results in such contact failures as open circuits, which reduces the production yield and reliability of the semiconductor devices.